A general-purpose standard IEEE 1149.1, also known as JTAG (Joint Test Action Group) according to the consortium that prepared the standard, has been created for testing different circuit boards and components and integrated circuits connected thereto. JTAG is a boundary scan method, in which an input signal is fed into a boundary pin of a circuit board and an output signal is measured from another boundary pin. The basic idea of JTAG is to transfer predetermined data sequences in series through IC components in a circuit board or in a part thereof and to sample the output data. As the topology and logical functions of the components of the circuit board to be tested are known in advance, an assumed output can also be determined. Test equipment may be used to compare the output data of a device under test DUT with the assumed output and if they correspond with one another, the device under test DUT operates correctly. If, in turn, the output data does not correspond with the assumed output, the tested circuit may be open, an outside signal may be connected thereto, or a component in the circuit may be defective. In such a case, the defect can typically be determined by running different test data sequences through the device under test and by analysing the obtained output using software included in the test equipment.
The JTAG standard determines for both the test equipment comprising a JTAG controller and the device under test DUT an identical test access port TAP interface, with a fixed synchronous line between them comprising at least five conductors for five compulsory signals: a test clock signal TCK, test mode select signal TMS, test data input TDI, test data output TDO and ground reference signal GND. Patent application EP 1,189,070 of the applicant describes a solution for avoiding the use of the fixed synchronous line between the test equipment and the device being tested, which widens the use of JTAG testing significantly. The solution described in the patent application is based on using in both the test equipment and the device under test DUT transceivers that adapt signals coming from the test access port TAP for transmission through an asynchronous transmission path in such a manner that received signals can again be synchronized in the format required by the test access port TAP. This type of solution enables the use of a wireless asynchronous transmission path in the transmission of test data, whereby it is for instance possible to test circuit boards and analyse faults with the test equipment by telecontrol without a fixed connection to the device being tested. Correspondingly, the solution makes it possible for instance to test circuit boards that are at a distance from each other by using telecontrol over the Internet.
A problem then arises in a situation, in which several simultaneous test processes need to be performed with the test device, but in which only one asynchronous connection (a radio link or a single Ethernet cable, for example) is available. Such a situation may occur for instance in testing a telecommunications satellite in orbit, when not only the number of asynchronous connections established for testing but also the time used for testing needs to be minimized. In the solution of EP 1,189,070, this type of testing arrangement would require that the test equipment have its own TAP interface and transmitter for each testing process, the test data of which should further be adapted to one transmission path. This makes the implementation of the test equipment heavy and expensive, and in addition to this, the adaptation of the test data of several testing processes on the same transmission path complicates the implementation of the uplink interface significantly.
Correspondingly, a problem also arises in a situation, in which one piece of test equipment is used in various tests over asynchronous connections utilizing different data transmission protocols. In the solution of EP 1,189,070, each data transmission protocol requires a transmitter of its own to adapt the test data to the used protocol. In this case, too, hardware implementation becomes complex and expensive.